The present invention relates to logic circuits, and more particularly to a GaAs single chip integrated logic circuit of ultrahigh speed and low power consumption.
A prior-art technique is discussed in, for example, IEEE Transactions on Electron Devices, ED-25, No. 6 (1978), pp. 628-639. FIG. 6 shows a DCFL (Direct Coupled FET Logic) circuit which is typical as a prior-art example and which is disclosed in the above literature. Here, the circuit is an inverter circuit which includes voltage source nodes 101 and 115, a load FET (field-effect transistor) 601 and a driving FET 602. The load FET 601 is a DFET (depletion type or normally-on type FET), while the driving FET 602 is an EFET (enhancement type or normally-off type FET). When, by way of example, a high level (for example, -0.35 V) is applied as an input signal from an input terminal 112 to the gate electrode of the driving FET 602, an output signal at a low level (for example, -0.85 V) appears at an output terminal 105. In addition, a NOR logic circuit is obtained by disposing a plurality of parallel FETs 602, each with its own gate input.
As a second prior-art example, there is an inverter circuit shown in FIG. 7. Referring to FIG. 7, an input signal is supplied from a terminal 112 to the gates of two driving FETs 702 and 703. A node 705 at which the EFET 703 and a resistor 704 are connected is connected to the gate of an EFET 701. An output signal is derived from a terminal 105. As in the first prior-art example, when the high level is supplied as the input signal, the low level appears at the terminal 105.
A high speed circuit discussed in IEEE Transactions on Electron Devices, ED-25, No. 6 (1970), pp. 628-639 is shown in FIG. 29. It has plus side voltage sources (of, for example, 0 V), 1151, 1152, and a minus side voltage source (of, for example, -2 V) 153, and it is constructed of field-effect transistors "FETs", 1101, 1102, 1104, 1105, and 1106, and a load element 1103 formed of a FET or the like. An input terminal 1155 is connected to the gate electrodes of the FETs 1101 and 1104. Another input terminal 1156 is similarly connected to the FETs 1102 and 1105. An output terminal 1157 is led out of the node between the source of the FET 1106 and the common drain electrodes of the FETs 1104, 1105.
The operation of this FIG. 29 circuit is in accordance with NOR logic that, when a logically high level (for example, -1.4 V) is applied to either the input terminal 1155 or 1156, a logically low level (for example, -2.0 V) appears at the output terminal 1157. The logical operation is chiefly determined by the FETs 1101, 1102 and the load element 1103. By way of example, when the input terminal 1155 is at the high level, current flows through the FET 1101 and the load element 1103, so that the potential of a lead 1120 lowers to approach the voltage of the minus side voltage source 1153. Accordingly, the logically low level (nearly equal to the voltage of the minus side voltage source) appears at the source of the FET 1106, namely, the output terminal 1157. In contrast, when the logically low level is applied to both the input terminals, no current flows through the load element 1103, so that the potential of the lead 1120 becomes nearly equal to the voltage of the plus side voltage source 1151 to turn on FET 1106, and the logically high level appears at the output terminal 1157, because FET's 1104 and 1105 are off.